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1 of 6 111799 features all-silicon time delay 7 independent buffered delays delay tolerance 2 ns four delays can be custom set between 3 ns and 10 ns three delays can be custom set between 9 ns and 40 ns delays are stable and precise economical auto-insertable, low profile surface mount 16-pin soic low-power cmos ttl/cmos-compatible vapor phase, ir and wave solderable custom specifications available quick turn prototypes pin assignment pin description in1 - in7 - inputs out1 ? out7 - outputs gnd - ground v cc - +5 volts description the ds1007 7-in-1 silicon delay line provides seven independent delay times which are set by dallas semiconductor to the customer?s specification. the delay times can be set from 3 ns to 40 ns with an accuracy of 2 ns at room temperature. the device is offered in both a 16-pin dip and a 16-pin soic. since the ds1007 is an all-silicon solution, better economy and reliability are achieved when compared to older methods using hybrid technology. the ds1007 reproduces the input logic state at the output after the fixed delay. dallas semiconductor can customize standard products to meet special needs. for special requests and rapid delivery, call (972) 371?4348. ds1007 7-1 silicon delay line www.dalsemi.com ds1007s 16-pin soic (300-mil) see mech. drawin g s sectio n in1 out1 in2 out2 in5 v cc in6 ou t 3 gnd in7 out6 ou t7 ou t4 in3 1 2 3 4 5 6 7 16 15 14 13 12 8 9 10 11 out5 in4 in1 out1 in2 out2 in5 v cc in6 out3 gnd in7 out6 out7 out4 in3 1 2 3 4 5 6 7 16 15 14 13 12 8 9 10 11 out5 in4 ds1007 16-pin dip (300-mil) see mech. drawings section
ds1007 2 of 6 logic diagram figure 1 part number delay table (t plh ) table 1 part # out1 out2 out3 out4 out5 out6 out7 ds1007-1 3ns 4ns 5ns 6ns 9ns 13ns 18ns ds1007-2 4 6 8 10 12 14 16 ds1007-3 3333101010 ds1007-4 4444121212 ds1007-5 5555151515 ds1007-6 6666202020 ds1007-7 7777252525 ds1007-8 8888303030 ds1007-9 9999353535 ds1007-10 10 10 10 10 40 40 40 ds1007-11 3468101214 ds1007-12 3468101520 ds1007-13 3468121520 ds1007-14 7777999 custom delays available. out 1 through out 4 can be custom set from 3 to 10 ns (leading edge only accuracy). out 5 through out 7 can be set from 9 to 40 ns (both leading and trailing edge accuracy).
ds1007 3 of 6 timing diagram: silicon delay line figure 2 test circuit figure 3
ds1007 4 of 6 absolute maximum ratings* voltage on any pin relative to ground -1.0v to +7.0v operating temperature 0 c to 70 c storage temperature -55 c to +125 c soldering temperature 260 c for 10 seconds short circuit output current 50 ma for 1 second * this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. dc electrical characteristics (0c to 70c; v cc = 5.0v 5%) parameter sym test condition min typ max units notes supply voltage v cc 4.75 5.00 5.25 v 1 high level input voltage v ih 2.2 v cc + 0.5 v 1 low level input voltage v il -0.5 0.8 v 1 input leakage current i i 0.0v v i v cc -1.0 1.0 ua active current i cc v cc =max; period=min. 40.0 70.0 ma 2 high level output current i oh v cc =min. v oh =2.4v -1.0 ma low level output current i ol v cc =min. v ol =0.5v 12.0 ma ac electrical characteristics (t a = 25c; v cc = 5v 5%) parameter symbol min typ max units notes input pulse width t wi 100% of t plh ns input to output (leading edge) t plh table 1 ns 3, 4, 5 power-up time t pu 100 ms 7 period 3 (t wi )ns6 capacitance (t a = 25c) parameter symbol min typ max units notes input capacitance c in 510pf
ds1007 5 of 6 notes: 1. all voltages are referenced to ground. 2. measured with outputs open. 3. v cc = 5v @25 c. delays accurate on rising edges within 2 ns. 4. see test conditions below. 5. all output delays in the same speed output tend to vary unidirectionally with temperature or voltage range (i.e., if out 2 slows down, all other outputs also slow down). 6. period specifications may be exceeded; however, accuracy will be application-sensitive (decoupling, layout, etc.). 7. t pu = 0 ms for out 1 through out 4. terminology period: the time elapsed between the leading edge of the first pulse and the leading edge of the following pulse. t wi (pulse width): the elapsed time on the pulse between the 1.5v point on the leading edge and the 1.5v point on the trailing edge, or the 1.5v point on the trailing edge and the 1.5v point on the leading edge. t rise (input rise time): the elapsed time between the 20% and the 80% point on the leading edge of the input pulse. t fall (input fall time): the elapsed time between the 80% and the 20% point on the trailing edge of the input pulse. t plh (time delay, rising): the elapsed time between the 1.5v point on the leading edge of the input pulse and the 1.5v point on the leading edge of the corresponding output pulse. test setup description figure 3 illustrates the hardware configuration used for measuring the timing parameters on the ds1007. the input waveform is produced by a precision pulse generator under software control. time delays are measured by a time interval counter (20 ps resolution) connected between the input and each output. each output is selected and connected to the counter by a vhf switch control unit. all measurements are fully automated, with each instrument controlled by a central computer over an ieee 488 bus.
ds1007 6 of 6 test conditions input: ambient temperature: 25c 3c supply voltage (v cc ): 5.0v 0.1v input pulse: high = 3.0v 0.1v low = 0.0v 0.1v source impedance: 50 ohm max. rise and fall time: 3.0 ns max. pulse width: 500 ns period: 1 s output: each output is loaded with the equivalent of one 74f04 input gate. delay is measured at the 1.5v level on the rising edge. note: above conditions are for test only and do not restrict the operation of the device under other data sheet conditions.
english ? ???? ? ??? ? ??? what's new products solutions design appnotes support buy company members ds1007 part number table notes: see the ds1007 quickview data sheet for further information on this product family or download the ds1007 full data sheet (pdf, 57kb). 1. other options and links for purchasing parts are listed at: http://www.maxim-ic.com/sales . 2. didn't find what you need? ask our applications engineers. expert assistance in finding parts, usually within one business day. 3. part number suffixes: t or t&r = tape and reel; + = rohs/lead-free; # = rohs/lead-exempt. more: see full data sheet or part naming conventions . 4. * some packages have variations, listed on the drawing. "pkgcode/variation" tells which variation the product uses. 5. part number free sample buy direct package: type pins size drawing code/var * temp rohs/lead-free? materials analysis ds1007-2 pdip;16 pin;300 dwg: 56-g5005-002a (pdf) use pkgcode/variation: p16-2 * 0c to +70c rohs/lead-free: no materials analysis ds1007-4 pdip;16 pin;300 dwg: 56-g5005-002a (pdf) use pkgcode/variation: p16-2 * 0c to +70c rohs/lead-free: no materials analysis ds1007-1 pdip;16 pin;300 dwg: 56-g5005-002a (pdf) use pkgcode/variation: p16-2 * 0c to +70c rohs/lead-free: no materials analysis
ds1007-5 pdip;16 pin;300 dwg: 56-g5005-002a (pdf) use pkgcode/variation: p16-2 * 0c to +70c rohs/lead-free: no materials analysis ds1007-6 pdip;16 pin;300 dwg: 56-g5005-002a (pdf) use pkgcode/variation: p16-2 * 0c to +70c rohs/lead-free: no materials analysis ds1007-7 pdip;16 pin;300 dwg: 56-g5005-002a (pdf) use pkgcode/variation: p16-2 * 0c to +70c rohs/lead-free: no materials analysis ds1007-8 pdip;16 pin;300 dwg: 56-g5005-002a (pdf) use pkgcode/variation: p16-2 * 0c to +70c rohs/lead-free: no materials analysis ds1007-9 pdip;16 pin;300 dwg: 56-g5005-002a (pdf) use pkgcode/variation: p16-2 * 0c to +70c rohs/lead-free: no materials analysis ds1007-11 pdip;16 pin;300 dwg: 56-g5005-002a (pdf) use pkgcode/variation: p16-2 * 0c to +70c rohs/lead-free: no materials analysis ds1007-10 pdip;16 pin;300 dwg: 56-g5005-002a (pdf) use pkgcode/variation: p16-2 * 0c to +70c rohs/lead-free: no materials analysis ds1007-12 pdip;16 pin;300 dwg: 56-g5005-002a (pdf) use pkgcode/variation: p16-2 * 0c to +70c rohs/lead-free: no materials analysis ds1007-13 pdip;16 pin;300 dwg: 56-g5005-002a (pdf) use pkgcode/variation: p16-2 * 0c to +70c rohs/lead-free: no materials analysis ds1007-14 pdip;16 pin;300 dwg: 56-g5005-002a (pdf) use pkgcode/variation: p16-2 * 0c to +70c rohs/lead-free: no materials analysis DS1007-LPP 0c to +70c rohs/lead-free: no
ds1007-3 pdip;16 pin;300 dwg: 56-g5005-002a (pdf) use pkgcode/variation: p16-2 * 0c to +70c rohs/lead-free: no materials analysis ds1007s-9 soic;16 pin;300 dwg: 56-g4009-001b (pdf) use pkgcode/variation: w16-2 * 0c to +70c rohs/lead-free: no materials analysis ds1007s-2+ soic;16 pin;300 dwg: 56-g4009-001b (pdf) use pkgcode/variation: w16+2 * 0c to +70c rohs/lead-free: yes materials analysis ds1007s-14+ soic;16 pin;300 dwg: 56-g4009-001b (pdf) use pkgcode/variation: w16+2 * 0c to +70c rohs/lead-free: yes materials analysis ds1007s-2+t&r soic;16 pin;300 dwg: 56-g4009-001b (pdf) use pkgcode/variation: w16+2 * 0c to +70c rohs/lead-free: yes materials analysis ds1007s-ac1/t&r 0c to +70c rohs/lead-free: no ds1007s-11/t&r soic;16 pin;300 dwg: 56-g4009-001b (pdf) use pkgcode/variation: w16-2 * 0c to +70c rohs/lead-free: no materials analysis ds1007s-9/t&r soic;16 pin;300 dwg: 56-g4009-001b (pdf) use pkgcode/variation: w16-2 * 0c to +70c rohs/lead-free: no materials analysis ds1007s-8/t&r soic;16 pin;300 dwg: 56-g4009-001b (pdf) use pkgcode/variation: w16-2 * 0c to +70c rohs/lead-free: no materials analysis ds1007s-7/t&r soic;16 pin;300 dwg: 56-g4009-001b (pdf) use pkgcode/variation: w16-2 * 0c to +70c rohs/lead-free: no materials analysis ds1007s-6/t&r soic;16 pin;300 dwg: 56-g4009-001b (pdf) use pkgcode/variation: w16-2 * 0c to +70c rohs/lead-free: no materials analysis
ds1007s-5/t&r soic;16 pin;300 dwg: 56-g4009-001b (pdf) use pkgcode/variation: w16-2 * 0c to +70c rohs/lead-free: no materials analysis ds1007s-4/t&r soic;16 pin;300 dwg: 56-g4009-001b (pdf) use pkgcode/variation: w16-2 * 0c to +70c rohs/lead-free: no materials analysis ds1007s-3/t&r soic;16 pin;300 dwg: 56-g4009-001b (pdf) use pkgcode/variation: w16-2 * 0c to +70c rohs/lead-free: no materials analysis ds1007s-7 soic;16 pin;300 dwg: 56-g4009-001b (pdf) use pkgcode/variation: w16-2 * 0c to +70c rohs/lead-free: no materials analysis ds1007s-1/t&r/ 0c to +70c rohs/lead-free: no ds1007s-10/t&r soic;16 pin;300 dwg: 56-g4009-001b (pdf) use pkgcode/variation: w16-2 * 0c to +70c rohs/lead-free: no materials analysis ds1007s-2 soic;16 pin;300 dwg: 56-g4009-001b (pdf) use pkgcode/variation: w16-2 * 0c to +70c rohs/lead-free: no materials analysis ds1007s-3 soic;16 pin;300 dwg: 56-g4009-001b (pdf) use pkgcode/variation: w16-2 * 0c to +70c rohs/lead-free: no materials analysis ds1007s-5 soic;16 pin;300 dwg: 56-g4009-001b (pdf) use pkgcode/variation: w16-2 * 0c to +70c rohs/lead-free: no materials analysis ds1007s-6 soic;16 pin;300 dwg: 56-g4009-001b (pdf) use pkgcode/variation: w16-2 * 0c to +70c rohs/lead-free: no materials analysis ds1007s-8 soic;16 pin;300 dwg: 56-g4009-001b (pdf) use pkgcode/variation: w16-2 * 0c to +70c rohs/lead-free: no materials analysis
ds1007s-10 soic;16 pin;300 dwg: 56-g4009-001b (pdf) use pkgcode/variation: w16-2 * 0c to +70c rohs/lead-free: no materials analysis ds1007s-11 soic;16 pin;300 dwg: 56-g4009-001b (pdf) use pkgcode/variation: w16-2 * 0c to +70c rohs/lead-free: no materials analysis ds1007s-12 soic;16 pin;300 dwg: 56-g4009-001b (pdf) use pkgcode/variation: w16-2 * 0c to +70c rohs/lead-free: no materials analysis ds1007s-13 soic;16 pin;300 dwg: 56-g4009-001b (pdf) use pkgcode/variation: w16-2 * 0c to +70c rohs/lead-free: no materials analysis ds1007s-14 soic;16 pin;300 dwg: 56-g4009-001b (pdf) use pkgcode/variation: w16-2 * 0c to +70c rohs/lead-free: no materials analysis ds1007s-1+ soic;16 pin;300 dwg: 56-g4009-001b (pdf) use pkgcode/variation: w16+2 * 0c to +70c rohs/lead-free: yes materials analysis ds1007s-1+t&r soic;16 pin;300 dwg: 56-g4009-001b (pdf) use pkgcode/variation: w16+2 * 0c to +70c rohs/lead-free: yes materials analysis ds1007s-1 soic;16 pin;300 dwg: 56-g4009-001b (pdf) use pkgcode/variation: w16-2 * 0c to +70c rohs/lead-free: no materials analysis didn't find what you need? contact us: send us an email copyright 2007 by maxim integrated products, dallas semiconductor ? legal notices ? privacy policy

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